School of Electronic and Communications Engineering

Mon, 20 Nov 2017 - DIT week 13

Home > Postgraduate students > Johannes Trein

Information for

Information about

Research

[AHFR logo] [prc logo] [CNRI logo]

Johannes Trein

Johannes Trein

e-mail: johannes.trein@web.de

Qualifications

BEng, Electrical and Electronic Engineering
Dipl.-Ing. (FH), Microelectronics Engineering
MPhil, Electronic and Communications Engineering

Research

FPGA investigation and implementation of a high speed real-time blob analysis

In the fields of image processing applications high resolution images with a maximum frame rate have to be processed. The necessary analysis of the pictures can only be determined in an ordinary CPU based system with high performance constraints. Here, a FPGA facilitates a pipelined and parallel analysis of the pictures in real time.

A blob analysis detects objects in an image which differ from the background and determines the object features like area, center of gravity, boundary box and perimeter. The algorithm facilitates an analysis in one pass with the parallel processing of up to 32 pixels, depending on the number of objects and picture noise. A frame rate of up to 500fps and resolutions of up to 16 megapixel-images are possible. Bandwidths of up to 1000 MPixel/sec are possible. The used XILINX Spartan III/E FPGA works at a clock frequency of 62.5MHz.

The research has been undertaken in cooperation with the ÁSystems research group at the Hochschule Darmstadt, University of Applied Sciences and Silicon Software GmbH which develops FPGA based frame grabber systems and therefore provides the image data and interface capabilities.

uSyst Silicon Software GmbH

The algorithm is fully implemented and verified. It is already used in numerous applications in industry.

Presentations at trade fairs.

The developed algorithm is used in an industrial environment. It has been presented at numerous machine vision trade fairs in Germany, Japan and Korea.

Research Supervisors

Dr. Andreas Schwarzbacher & Dr. Bernhard Hoppe

Publications

J. Trein, A. Th. Schwarzbacher, B. Hoppe, K.-H. Noffz and T. Trenschel, "The FPGA implementation and investigation of a real-time blob analysis algorithm," Irish Systems and Signals Conference, Derry, N. Ireland, pp. 121-126, September 2007.pdf file

J. Trein, A. Th. Schwarzbacher and B. Hoppe, "The development of a binary pseudo random number generator with controllable output density," Irish Systems and Signals Conference, Derry, N. Ireland, pp. 235-240, September 2007.pdf file

J. Trein, A. Th. Schwarzbacher and B. Hoppe, "FPGA Implementation of a Single Pass Real-Time Blob Analysis Using Run Length Encoding," MPC-Workshop, Ravensburg-Weingarten, Germany, February 2008.pdf file

J. Trein, A. Th. Schwarzbacher, B. Hoppe and K.-H. Noffz, "A Hardware Implementation of a Run Length Encoding Compression Algorithm with Parallel Inputs," Irish Signals and Systems Conference, Galway, June 2008

Thesis

J. Trein, "FPGA Implementation of a Real-Time Blob Analysis Algorithm for Object Detection and Feature Extraction", Master Thesis, Dublin Institute of Technology, February 2009